Low latency memory access control for non-volatile memories

A method comprising:

• providing a bank of non-volatile memory cells configured into a plurality of banklets, wherein each banklet in the plurality of banklets is separately able to be enabled independently of the other banklets in the bank of non-volatile memory cells;
• providing peripheral banklet circuitry, coupled to the bank of non-volatile memory cells, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets;
• and
• providing banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet;
• and
• fabricating an integrated circuit device comprising the provided bank, peripheral banklet circuitry, and banklet select circuitry.

A computer, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory comprises:
• a bank of non-volatile memory cells configured into a plurality of banklets, wherein each banklet in the plurality of banklets is separately able to be enabled independently of the other banklets in the bank of non-volatile memory cells;
• peripheral banklet circuitry, coupled to the bank of non-volatile memory cells, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets;
• and
• banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.