US 9,286,958 B2Granted

Memory with termination circuit

AssigneeRenesas Electronics Corporation

InventorsMasayasu Komyo, Yoichi Iizuka

Life of this patent

Estimating the term…

Loading patent…

Abstract

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Claims9

Dependent claims

A semiconductor integrated circuit comprising:

a first external terminal connected to a first external line;
a second external line different from the first external line;
and
a transmitter-receiver that transmits and receives data to and from outside by the first external terminal and transmits a first control signal by the second external line, wherein:
when the data is received by the first external terminal, the transmitter-receiver sets the first control signal for a first termination circuit provided outside to have a first potential level,
when the data is transmitted by the first external terminal, the transmitter-receiver sets the first control signal for the first termination circuit to have a second potential level, and
when another data is transmitted after the data is transmitted, the transmitter-receiver keeps the first control signal to have the second potential level when a data transmission interval from a time when the data is transmitted to a time when the other data is transmitted is equal to or smaller than a first threshold and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/579,364Filed 22 Dec 2014 · continuation
Priority: JP 2009-2068818 Sep 2009
Published: US 2015/0109869 A123 Apr 2015
Granted: 15 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…
G11C 7/02
Arrangements for writing information into, or reading information out from, a digital store: with means for avoiding parasitic signals
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits

Family

Application12/876,747Parent of this continuation · filed 7 Sep 2010
Application13/271,819Parent of this continuation · filed 12 Oct 2011
Application14/031,462Parent of this continuation · filed 19 Sep 2013
US 2015/0109869 A1Pre-grant publication · published 23 Apr 2015
US 8,952,719 B2Parent of this continuation
US 8,558,572 B2Parent of this continuation
US 8,102,186 B2Parent of this continuation
US 2011/0057720 A1Published application
US 2012/0026812 A1Published application
US 2014/0016401 A1Published application
US 9,286,958 B2This patent

From the US filing history. Foreign family members aren’t listed.