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US 9,286,954 B2Granted
Buffer circuit of semiconductor apparatus
AssigneeSK hynix Inc.
InventorJin Ha Hwang
Life of this patent
Estimating the term…
Abstract
A buffer circuit of a semiconductor apparatus includes a sensing circuit configured to sense input signals according to a data strobe signal, generate latch control signals, provide the latch control signals at nodes, and remove parasitic components of the nodes in response to a clock signal; and a latch circuit configured to generate and latch output data in response to the latch control signals.
Claims7
A buffer circuit of a semiconductor apparatus, comprising:
- a sensing unit configured to sense a voltage level difference of differential input signals and generate latch control signals, during an activation period of a data strobe signal;
- an activation unit configured to activate a current path of the sensing unit in response to the data strobe signal;
- a compensation unit configured to serve as a negative impedance component in response to a clock signal and remove parasitic components of nodes;
- and
- a latch circuit configured to generate and latch output data in response to the latch control signals.
2 more elements
A buffer circuit of a semiconductor apparatus, comprising:
- a sensing unit configured to electrically couple with a power supply terminal, sense a voltage level difference of differential input signals during an activation period of a data strobe signal, generate latch control signals, and provide the latch control signals at nodes;
- an activation unit configured to electrically couple with a ground terminal, and activate a current path of the sensing unit in response to the data strobe signal;
- an input unit configured to electrically couple with the activation unit, and receive the differential input signals;
- and
- a compensation unit electrically coupled with the sensing unit and the input unit, and configured to remove parasitic components of the nodes in response to a clock signal.
2 more elements
A buffer circuit of a semiconductor apparatus, comprising:
- a sensing unit configured to sense a voltage level difference of differential input signals during an activation period of a data strobe signal, generate and provide a first differential latch control signal at a first node, and generate and provide a second differential latch control signal at a second node;
- an activation unit configured to activate a current path of the sensing unit in response to the data strobe signal;
- and
- a capacitor electrically coupled with the first node and the second node, and configured to remove parasitic components of the first and second nodes in response to a clock signal.
1 more element
Dependencies are inferred from the claim text.