SRAM with two-level voltage regulator

A programmable logic device, comprising:

• a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device;
• a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage, wherein the SRAM cells are powered through a coupling to the first power supply node;
• and
• a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device
• wherein the first power supply node comprises a voltage rail, and wherein the two-level voltage regulator comprises a differential amplifier configured to drive a gate of a transistor coupled between a second power supply node and the voltage rail responsive to a difference between a feedback voltage and a reference voltage.

A method, comprising:

• powering an SRAM cell within a programmable logic device with a reduced power supply voltage;
• while the SRAM cell is powered by the reduced power supply voltage, writing to the SRAM cell to configure the programmable logic device by accessing the SRAM cell through an access transistor having its gate charged by the reduced power supply voltage;
• and
• operating the configured programmable logic device while the SRAM cell is powered with an increased power supply voltage that is greater than the reduced power supply voltage;
• and
• reading a stored value in the SRAM cell while the SRAM cell is powered with the increased power supply voltage, wherein reading the stored value in the SRAM cell occurs through the access transistor by charging the gate of the access transistor to an operating voltage (VCC) that is lower than the reduced power supply voltage.

A method, comprising:

• powering an SRAM cell within a programmable logic device with a reduced power supply voltage;
• while the SRAM cell is powered by the reduced power supply voltage, writing to the SRAM cell to configure the programmable logic device by accessing the SRAM cell through an access transistor having its gate charged by the reduced power supply voltage;
• and
• operating the configured programmable logic device while the SRAM cell is powered with an increased power supply voltage that is greater than the reduced power supply voltage wherein powering the SRAM cell with the reduced power supply voltage comprises driving a gate of a transistor coupled between a voltage rail carrying the reduced power supply voltage and a power supply node carrying a power supply voltage that is greater than the increased power supply voltage, wherein driving the gate of the transistor is responsive to a comparison of a feedback voltage to a reference voltage.