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US 9,286,950 B2Granted
Semiconductor chip, memory chip, semiconductor package and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorBoseong Kim
Life of this patent
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Abstract
A semiconductor chip includes a plurality of signal and power pads; and a plurality of chip selection pads, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad.
Claims40
A semiconductor package comprising:
- first and second memory chips configured to be stacked,
- wherein one memory chip of the first and second memory chips comprises a plurality of signal and power pads and a plurality of chip selection pads,
- wherein first pads of the chip selection pads are electrically connected to a device external to the one memory chip and second pads of the chip selection pads are electrically isolated from the device.
A semiconductor package comprising:
- a plurality of memory chips configured to be stacked;
- and
- a controller chip configured to control the plurality of memory chips,
- wherein one memory chip of the first and second memory chips comprises a plurality of signal and power pads and a plurality of chip selection pads,
- wherein the controller chip comprises a plurality of control chip selection pads, a first control chip selection pad of the plurality of control chip selection pads is connected with first chip selection pads of first memory chips of the plurality of memory chips, and a second control chip selection pad of the plurality of control chip selection pads is connected with second chip selection pads of second memory chips, different from the first memory chips, of the plurality of memory chips.
2 more elements
A semiconductor package comprising:
- a controller chip configured to control a memory;
- a plurality of signal and power nodes electrically connected with a plurality of signal and power pads of the controller chip;
- and
- a plurality of chip selection nodes electrically connected with a plurality of chip selection pads of the controller chip,
- wherein a chip selection pad of the plurality of chip selection nodes comprises a normal pad and an inverse pad, and
- wherein the chip selection node of the plurality of chip selection nodes comprises the normal node and the inverse node, at least one of the normal node and the inverse node is connected with the normal pad and the inverse pad.
3 more elements
A memory controller chip comprising:
- a plurality of signal and power pads;
- and
- a plurality of chip selection pads including a normal pad and an inverse pad, the normal pad and the inverse pad being a differential pair,
- wherein the chip selection pads are independently controlled to have a logically high or a logically low value, and
- wherein a combination of the chip selection pads is output as a chip selection signal.
2 more elements
A memory system comprising:
- first and second memory chips configured to be stacked;
- and
- a memory controller chip configured to control the first and second memory chips,
- wherein one of the first and second memory chips is configured to communicate with the memory controller chip via a plurality of signal and power pads and a plurality of chip selection pads,
- wherein one of the first and second memory chips and the memory controller chip includes a normal chip selection pad and an inverse chip selection pad.
2 more elements
A solid state drive comprising:
- a substrate;
- a plurality of memory packages;
- a controller package;
- and
- a connector,
- wherein at least one of the plurality of memory packages comprises first and second memory chips, the first and second memory chips are configured to be stacked, and
- wherein the controller package comprises a controller chip, the controller chip configured to select the at least one of the plurality of memory packages using a smaller number of signals than a total number of signals of the at least one of the plurality of memory packages.
4 more elements
Dependencies are inferred from the claim text.