Semiconductor memory
AssigneeRenesas Electronics Corporation
InventorHiroyuki Takahashi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair, in which the sense amplifier has precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors having a diffusion layer formed integrally with the diffusion layer of the precharging transistors for selectively connecting the plurality of bit line pairs to a common bus line.
Claims16
A semiconductor memory comprising:
- a memory cell array having a plurality of memory cells;
- a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array;
- and
- sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair,
- wherein the sense amplifier includes:
- precharging transistors each having a diffusion layer and precharging the bit line pair;
- and
- switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.
A semiconductor memory comprising:
- a memory cell array having a plurality of memory cells;
- a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array;
- amplifying transistors which are disposed in plurality corresponding to the plurality of bit line pair for amplifying a potential difference between the bit line pair;
- and
- switching transistors selectively connecting the plurality of bit line pairs to a common bus line,
- wherein a channel width direction of two or more of the switching transistors sharing the gate is along a longitudinal direction of the gate.
Dependencies are inferred from the claim text.