Display panel self-refresh entry and exit

A method, comprising:

• negotiating one or more component capabilities of a first component by a second component via an interface, wherein the interface includes a primary link, an auxiliary link, and a hot plug detect (HPD) link;
• and receiving a timing reference signal by the first component;
• generating a synchronization signal by the first component, wherein the synchronization signal is dependent upon the timing reference signal;
• transmitting, by the first component, the synchronization signal to a second component via the HPD link;
• generating, by the second component, a timing signal dependent upon the transmitted synchronization signal;
• and transmitting, by the second component, through the interface, data to the first component dependent upon the generated timing signal.

A system, comprising:

• a memory;
• a first processor coupled to the memory, wherein the first processor includes a first timing generator circuit;
• a second processor coupled to the first processor through an interface, wherein the second processor includes a second timing generator circuit;
• and
• a display coupled to the second processor;
• wherein the first processor is configured to negotiate one or more capabilities of the second processor via the interface, wherein the interface includes a primary link,
• an auxiliary link, and a hot plug detect (HPD) link;
• wherein the second timing generator circuit is configured to:
• receive a first timing signal;
• and
• generate a synchronization signal dependent upon the first timing signal;
• wherein the second processor is configured to transmit the synchronization signal to the first processor via the HPD link;
• wherein the first timing circuit is configured to generate a second timing signal dependent upon the synchronization signal;
• and
• wherein the first processor is configured to transmit data via the interface to the second processor dependent upon the second timing signal.

A method, comprising:

• performing one or more refresh operations on a display by a first processor;
• sending a command to resume operation to the first processor by a second processor via an interface, wherein the interface includes primary link, an auxiliary link, and a hot plug detect (HPD) link;
• in response to determining the sending of the command to resume operation has completed, sending at least one parameter to the first processor by the second processor via the interface, wherein the at least one parameter includes information indicative of a new clock frequency;
• transmitting a synchronization signal to the first processor by the second processor via the interface in response to determining the sending of the at least one parameter has completed;
• wherein transmitting the synchronization signal comprises sending the synchronization signal via the HPD link;
• and
• adjusting a timing generator circuit of the first processor dependent upon the synchronization signal.