Repairable GOA circuit and display device for flat panel display

A repairable gate on array (GOAO circuit for flat panel display, comprising multiple GOA units cascaded with each other, charging an n-th level horizontal scanning line in the display region according to the n-th level GOA unit, both ends of the n-th level horizontal scanning line being connected with one said n-th level GOA unit, the n-th level GOA unit comprising a pull-up circuit, a pull-down circuit, a pull-down holding circuit, a pull-up control circuit, a boost strap capacitor, and a first thin film transistor;

• the pull-up circuit, the pull-down circuit, the pull-down holding circuit, and a boost strap capacitor being respectively connected with a gate signal point and the n-th level horizontal scanning line, the pull-up control circuit being connected with the gate signal point;
• the gate of the first thin film transistor inputting a level clock signal, the drain and the source thereof being respectively connected with the gate signal point and the n-th level horizontal scanning line;
• wherein, when the n-th level GOA unit is working normally, at least one of the drain and the source of the first thin film transistor keeps disconnected with the n-th level GOA unit, when the pull-down holding circuit is abnormal, isolate the pull-down holding circuit from the n-th level GOA unit, and completely connect the first thin film transistor to the n-th level GOA unit to finish repair, wherein the pull-down holding circuit further comprises:
• a fourth thin film transistor, the gate thereof being connected with a first circuit point, the drain and the source thereof being respectively connected with the n-th level horizontal scanning line and inputting a DC low voltage;
• a fifth thin film transistor, the gate thereof being connected with a second circuit point, the drain and the source thereof being respectively connected with the n-th level horizontal scanning line and inputting the DC low voltage;
• a sixth thin film transistor, the gate thereof being connected with the first circuit point, the drain and the source thereof being respectively connected with the (n−1)-th level horizontal scanning line and inputting the gate signal point;
• a seventh thin film transistor, the gate thereof being connected with the second circuit point, the drain and the source thereof being respectively connected with the (n−1)-th level horizontal scanning line and inputting the gate signal point;
• an eighth thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source thereof being respectively connected with the first circuit point and inputting the DC low voltage;
• an ninth thin film transistor, the gate thereof being connected with the gate signal point, the drain and the source thereof being respectively connected with the second circuit point and inputting the DC low voltage;
• an tenth thin film transistor, the gate thereof inputting a first clock signal, the drain and the source thereof inputting the first clock signal and being respectively connected with the first circuit point;
• an eleventh thin film transistor, the gate thereof inputting a second clock signal, the drain and the source thereof inputting the first clock signal and being respectively connected with the first circuit point;
• an twelfth thin film transistor, the gate thereof inputting the second clock signal, the drain and the source thereof respectively inputting the second clock signal and being connected with the second circuit point;
• and an thirteenth thin film transistor, the gate thereof inputting the first clock signal, the drain and the source thereof respectively inputting the second clock signal and being connected with the second circuit point;
• wherein, when working, the frequencies of the first clock signal and the second clock signal are lower than the level clock signal, and first circuit point and the second circuit point are alternately charged to the high potential by the first clock signal and the second clock signal.

A repairable gate on array (GOA) circuit for flat panel display, comprising multiple GOA units cascaded with each other, charging an n-th level horizontal scanning line in the display region according to the n-th level GOA unit, both ends of the n-th level horizontal scanning line being connected with one said n-th level GOA unit, the n-th level GOA unit comprising a pull-up circuit, a pull-down circuit, a pull-down holding circuit, a pull-up control circuit, a boost strap capacitor, and a first thin film transistor;

• the pull-up circuit, the pull-down circuit, the pull-down holding circuit, and a boost strap capacitor being respectively connected with a gate signal point and the n-th level horizontal scanning line, the pull-up control circuit being connected with the gate signal point;
• the gate of the first thin film transistor inputting a level clock signal, the drain and the source thereof being respectively connected with the gate signal point and the n-th level horizontal scanning line;
• wherein, when the n-th level GOA unit is working normally, at least one of the drain and the source of the first thin film transistor keeps disconnected with the n-th level GOA unit, when the pull-down holding circuit is abnormal, isolate the pull-down holding circuit from the n-th level GOA unit, and completely connect the first thin film transistor to the n-th level GOA unit to finish repair;
• wherein, the pull-down holding circuit is isolated from the n-th level GOA unit by laser fusing;
• wherein, the metal wires connected with the drain or the source of the first thin film transistor intersect with the metal wires connected with the corresponding gate signal point or the n-th level horizontal scanning line, which are separated by an insulating layer;
• wherein, the first thin film transistor is completely connected to the n-th level GOA unit by laser welding;
• wherein, the pull-up control circuit comprises:
• a second thin film transistor, the gate thereof being connected with the (n−2)-th level horizontal scanning line, the drain and the source thereof being respectively connected with the (n−2)-th level horizontal scanning line and the gate signal point;
• and a third thin film transistor, the gate thereof being connected with the (n−1)-th level horizontal scanning line, the drain and the source thereof being respectively connected with the (n−1)-th level horizontal scanning line and the gate signal point.