Efficient packet handling, redirection, and inspection using offload processors

A packet handling system, comprising:

• at least one main processor coupled to a system bus and to a memory bus by a memory controller,
• a plurality of offload processors disposed on hardware modules directly connected to a memory bus and configured to provide security related services on packets received over the memory bus by operation of the memory controller prior to redirection to the main processor;
• an arbiter disposed on at least one of the hardware modules and connected to each of the plurality of offload processors of its hardware module, the arbiter configured to schedule resource priority for instructions or data received from the memory bus by operation of the memory controller;
• a first virtual switch disposed on at least one of the hardware modules in communication with both the main processor and the plurality of offload processors by operation of the memory controller using the memory bus, with the first virtual switch configured to receive memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter;
• and
• a second virtual switch coupled to the system bus and configured to receive the packets and direct the packets to at least the first virtual switch by operation of the memory controller.