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US 9,286,433 B2Granted
Method of fast analog layout migration
AssigneesSynopsys Taiwan Co., Ltd., Synopsys, Inc.
InventorsTung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
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Abstract
A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
Claims40
A computer implemented method of forming an integrated circuit (IC) layout, the method comprising:
- using the computer, automatically forming a constraint tree when the computer is invoked to receive a first layout of the IC, the constraint tree comprising a plurality of constraint nodes describing placement constraints based on the first layout, wherein the placement constraints comprise:
- one or more matching constraints,
- one or more symmetry constraints, and
- one or more other constraints;
- and
- generating, using the computer, a second layout of the IC, the second layout of the IC conforming with the constraints of the constraint tree, wherein:
- device modules of the second layout subject to the matching constraints are placed with a placement pattern extracted from the corresponding device modules of the first layout without exploring other placement patterns,
- device modules of the second layout subject to the symmetry constraints are placed with a placement pattern extracted from the corresponding device modules of the first layout without exploring other placement patterns, and
- device modules of the second layout subject to the other constraints are placed with a placement pattern which is generated as a result of exploring alternative placement patterns, and is different from the placement pattern of the corresponding device modules of the first layout.
6 more elements
A system for forming an integrated circuit (IC) layout, the system comprising:
- a processor, and
- a memory storing a set of instructions which when executed by the processor configures the processor to:
- automatically form a constraint tree for a first layout of the IC when the processor is invoked to receive the first layout of the IC, the constraint tree comprising a plurality of constraint nodes describing placement constraints based on the first layout, wherein the placement constraints comprise:
- one or more matching constraints,
- one or more symmetry constraints, and
- one or more other constraints;
- and
- generate a second layout of the IC, the second layout of the IC conforming with the constraints of the constraint tree, wherein:
- device modules of the second layout subject to the matching constraints are placed with a placement pattern extracted from the corresponding device modules of the first layout without exploring other placement patterns,
- device modules of the second layout subject to the symmetry constraints are placed with a placement pattern extracted from the corresponding device modules of the first layout without exploring other placement patterns, and
- device modules of the second layout subject to the other constraints are placed with a placement pattern which is generated as a result of exploring alternative placement patterns, and is different from the placement pattern of the corresponding device modules of the first layout.
8 more elements
Dependencies are inferred from the claim text.