Boundary based power guidance for physical synthesis

A system to obtain a physical design of an integrated circuit from a logical design, the system comprising:

• a memory device configured to store a logical design;
• and
• a processor configured to execute a synthesis engine, the processor being further configured to:
• perform a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget;
• compute power assertions;
• perform a re-synthesis using the timing constraints and the power assertions to obtain a new physical design;
• compare the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design;
• reduce a weighting of the power assertions relative to the timing constraints based on the degradation;
• and
• iteratively perform the re-synthesis, compare the new physical design with the baseline physical design, and reduce the weighting until the degradation is below a threshold value, wherein the processor is configured to compare the new physical design and the baseline physical design based on determining a baseline quality of result (QOR) for the baseline physical design and a new QOR for the new physical design and using a difference between the baseline QOR and the new QOR as a measure of the degradation.