Method and apparatus for testing
AssigneeInternational Business Machines Corporation
InventorsGabor Bobok, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Gil Shurek
Life of this patent
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Abstract
A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.
Claims18
A computer-implemented method performed by a computerized device, comprising:
- receiving a design;
- receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design;
- selecting whether a verification engine to be used is a simulation engine or a formal analysis engine;
- translating the scenario to an input for the verification engine as selected;
- activating the verification engine as selected, and providing the input to the verification engine, whereby the verification engine outputting a result;
- and
- displaying the result.
A computerized apparatus having a processor, the processor being adapted to perform the steps of:
- receiving a design;
- receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design;
- selecting whether a verification engine to be used is a simulation engine or a formal analysis engine;
- translating the scenario to an input for the verification engine as selected;
- activating the verification engine and providing the input to the verification engine, whereby the verification engine outputting a result;
- and
- displaying the result.
A computer program product comprising a non-transitory computer readable storage medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform a method comprising:
- receiving a design;
- receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design;
- selecting whether a verification engine to be used is a simulation engine or a formal analysis engine;
- translating the scenario to an input for the verification engine as selected;
- activating the verification engine and providing the input to the verification engine, whereby the verification engine outputting a result;
- and
- displaying the result.
Dependencies are inferred from the claim text.