Method, structure and design structure for customizing history effects of SOI circuits

A process for manufacturing an integrated circuit, the process comprising:

• translating inputs into a design structure embodied in a machine readable storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format;
• and fabricating the integrated circuit defined by the design structure having manufacturing data, wherein the integrated circuit includes:
• a high-leakage dielectric on each of sides of a segmented field effect transistor (FET) comprised of active silicon islands and gate electrodes thereon;
• and
• a low-leakage dielectric on and in contact with a top surface of the active silicon islands, adjacent the high-leakage dielectric, a top surface of the high-leakage dielectric being at a coplanar level as the top surface of the active silicon islands;
• and
• a gate electrode material is within a divot of a shallow trench isolation material and is in direct contact with and between a portion of the shallow trench isolation material and the high-leakage dielectric, wherein the high-leakage dielectric is within the divot and on a side surface of the active silicon islands, wherein:
• the high-leakage dielectric, the low-leakage dielectric, the gate electrode material, and the shallow trench isolation material are completely above a buried oxide (BOX) layer;
• the gate electrodes are directly in contact with the shallow trench isolation material;
• and
• top surfaces of the gate electrode material and the shallow trench isolation material are formed at the coplanar level as the top surfaces of the high-leakage dielectric and the active silicon islands.