Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method of using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the FPGA being associated with a target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd, the method comprising:

• in a defined cycle of time, applying a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
• and
• said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• and
• wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the method further comprising:
• hiding a refresh of the target DRAM memory by
• scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory,
• forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
• stopping a DUT clock while the refresh of the target memory is occurring, and restarting the DUT clock after the refresh of the target memory has finished.

A method of using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT), the DUT including a device memory having a number of input ports, the FPGA being associated with a target memory having a second number of input ports, said second number being less than said first number, the method comprising:

• applying a given set of inputs to the device memory via the input ports of the device memory at a frequency Fd and in a defined cycle of time;
• and
• applying said given set of inputs to the target memory via the input ports of the target memory at a frequency Ft, wherein Ft is greater than Fd, to apply all of said given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory,
• wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the target DRAM memory is refreshed at determined times, and the method further comprising:
• hiding the refresh of the target memory by hyper clocking the target memory so that the target memory and the DUT memory operate at different frequencies, and hiding the refresh of the target memory by using the frequency difference between the DUT memory operations and the target memory operations.

A system for simulating operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the system comprising:

• at least one Field Programmable Gate Array (FPGA);
• a target memory communicatively associated with the FPGA, the target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
• a controller for applying in a defined cycle of time, a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
• said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• and wherein:
• the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory;
• and
• the target memory controller hides a refresh of the target DRAM memory by scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory,
• forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
• stopping a DUT clock while the refresh of the target memory is occurring, and restarting the DUT clock after the refresh of the target memory has finished.

A system for simulating operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the system comprising:

• at least one Field Programmable Gate Array (FPGA);
• a target memory communicatively associated with the FPGA, the target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
• a controller for applying in a defined cycle of time, a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
• said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• and wherein:
• the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the target DRAM memory is refreshed at determined times;
• and
• the target memory controller hides the refresh of the target memory by hyper clocking the target memory so that the target memory and the DUT memory operate at different frequencies, and hiding the refresh of the target memory by using the frequency difference between the DUT memory operations and the target memory operations.

A method of modeling cycle accurate and cycle reproducible memory for a Field Programmable Gate Array (FPGA) based hardware accelerator, the method comprising:

• in a defined cycle of time, applying a given set of inputs to a memory of a device under test (DUT) operating in device clock cycles at a frequency Fd, the memory of the DUT having a first number of input ports, and to a target memory operating in target clock cycles at a frequency Ft, said target memory having a second number of input ports, said second number being less than said first number, and Ft being greater than Fd, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
• said applying including using said extra clock cycles of the target memory for using said more target memory clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• creating a cycle accurate model of the DUT memory by separating a DUT memory interface protocol from a target memory storage array, including
• using one or more first, stoppable device memory clocks to operate the device memory at the frequency Fd;
• using one or more target memory clocks to operate the target memory at the frequency Ft;
• at defined times, resetting the device memory to a defined, non-zero device memory state;
• and
• stopping the one or more device memory clocks while resetting the device memory to the defined non-zero device memory state to provide the device memory with cycle reproducibility;
• and
• wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the method further comprising:
• hiding a refresh of the target DRAM memory by
• scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory,
• forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
• stopping a DUT clock while the refresh of the target memory is occurring, and restarting the DUT clock after the refresh of the target memory has finished.

A method of modeling cycle accurate and cycle reproducible memory for a Field Programmable Gate Array (FPGA) based hardware accelerator, the method comprising:

• in a defined cycle of time, applying a given set of inputs to a memory of a device under test (DUT) operating in device clock cycles at a frequency Fd, the memory of the DUT having a first number of input ports, and to a target memory operating in target clock cycles at a frequency Ft, said target memory having a second number of input ports, said second number being less than said first number, and Ft being greater than Fd, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
• said applying including using said extra clock cycles of the target memory for using said more target memory clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• creating a cycle accurate model of the DUT memory by separating a DUT memory interface protocol from a target memory storage array, including
• using one or more first, stoppable device memory clocks to operate the device memory at the frequency Fd;
• using one or more target memory clocks to operate the target memory at the frequency Ft;
• at defined times, resetting the device memory to a defined, non-zero device memory state;
• and stopping the one or more device memory clocks while resetting the device memory to the defined non-zero device memory state to provide the device memory with cycle reproducibility;
• and
• wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the target DRAM memory is refreshed at determined times, and the method further comprising:
• hiding the refresh of the target memory by hyper clocking the target memory so that the target memory and the DUT memory operate at different frequencies, and hiding the refresh of the target memory by using the frequency difference between the DUT memory operations and the target memory operations.

A system to model cycle accurate and cycle reproducible memory for a Field Programmable Gate Array (FPGA) based hardware accelerator device, the system comprising:

• at least one Field Programmable Gate Array (FPGA);
• a DUT controller for applying, in a defined cycle of time, a given set of inputs to a memory of a device under test (DUT) operating in device clock cycles at a frequency Fd, the DUT having a first number of input ports;
• a target memory communicatively associated with the FPGA, the target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
• one or more, stoppable device memory clocks to operate the memory of the DUT at a frequency Fd;
• one or more target memory clocks to operate the target memory at the frequency Ft;
• the DUT controller is configured for stopping the one or more device memory clocks under defined conditions, for resetting the device memory at defined times to a defined, non-zero device memory state, and for stopping the one or more device memory clocks while resetting the device memory to the defined non-zero device memory state to provide the device memory with cycle reproducibility;
• and
• a target memory controller for applying said given set of inputs to the target memory via the input ports of the target memory in said defined cycle of time, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state, including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to create a cycle accurate model of the DUT memory by separating a DUT memory interface protocol from a target memory storage array, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state;
• and wherein:
• the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory;
• and
• the target memory controller hides a refresh of the target DRAM memory by scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory, and forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
• the system further comprises a mechanism to stop the DUT clocks while the refresh of the target memory is occurring, and to restart the DUT clocks after the refresh of the target memory has finished.