Method and apparatus for lowering I/O power of a computer system and computer system
AssigneeInternational Business Machines Corporation
InventorsYu Li, Wen Bo Shen, Yan Qi Wang, Yudong Yang
Life of this patent
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Abstract
The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.
Claims22
A method for lowering I/O power of a computer system, comprising:
- buffering a plurality of ways of data to be sent to a bus;
- encoding each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both integers larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
- wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one;
- and
- sending said plurality of ways of data encoded to said bus.
An apparatus for lowering I/O power of a computer system, comprising:
- an original data buffer configured to buffer a plurality of ways of data to be sent to a bus;
- an encoder configured to encode each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both in larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
- wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one;
- and
- an encoded data buffer configured to buffer said plurality of ways of data encoded in order to send them to said bus.
A computer system, comprising:
- a CPU;
- an I/O device;
- a bus configured to transfer data between said CPU and said I/O device;
- an original data buffer configured to buffer a plurality of ways of data to be sent to the bus;
- an encoder configured to encode each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both integers larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
- wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one;
- and
- an encoded data buffer configured to buffer said plurality of ways of data encoded in order to send them to said bus.
Dependencies are inferred from the claim text.