US 9,286,256 B2Granted

Sharing data crossbar for reads and writes in a data cache

AssigneeNVIDIA Corporation

InventorsAlexander L. Minkin, Steven J. Heinrich, Rajeshwaran Selvanesan, Stewart Glenn Carlton, John R. Nickolls

Life of this patent

Estimating the term…

Loading patent…

Abstract

The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.

Claims28

Dependent claims

A method for processing a plurality of data requests received from a client entity within a computing device, the method comprising:

determining an instruction type and an address associated with each data request included in the plurality of data requests, wherein the instruction type comprises a local, shared, or global instruction type, and the plurality of data requests are directed towards a memory unit that includes a plurality of memory banks;
identifying a subset of the plurality of data requests to process together, the subset of data requests comprising at least two data requests for different memory banks of the memory unit, each of the at least two data requests comprising either a shared instruction type or global instruction type;
processing, by a single arbiter, the subset of data requests within a same single clock cycle of a clock to which arbiter operations are synchronized;
and
scheduling a cache crossbar unit either to transmit data associated with at least one data request included in the subset of data requests to the memory unit at a second clock cycle or to transmit data associated with the at least one data request retrieved from the memory unit at the second clock cycle.

2 more elements

A computer system, the computer system comprising:

one or more client subsystems;
a memory unit;
a cache crossbar unit;
and
a single arbiter configured to:
determine an instruction type and an address associated with each data request included in the plurality of data requests;
determine an instruction type and an address associated with each data request included in the plurality of data requests, wherein the instruction type comprises a local, shared, or global instruction type, and the plurality of data requests are directed towards a memory unit that includes a plurality of memory banks;
identify a subset of the plurality of data requests to process together based on each data request in the subset of data requests comprising either a data request associated with a shared instruction type or a data request associated with a global instruction type, the subset of data requests comprising at least two data requests;
identify a subset of the plurality of data requests to process together, the subset of data requests comprising at least two data requests for different memory banks of the memory unit, each of the at least two data requests comprising either a shared instruction type or global instruction type;
process the subset of data requests within a same single clock cycle of a clock to which arbiter operations are synchronized;
and
schedule the cache crossbar unit either to transmit data associated with at least one data request included in the subset of data requests to the memory unit at a second clock cycle or to transmit data associated with the at least one data request retrieved from the memory unit at the second clock cycle.

9 more elements

Dependencies are inferred from the claim text.