US 9,286,250 B2Granted

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsDaijiro Harada, Takashi Utsumi

Life of this patent

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Abstract

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Claims8

Dependent claims

A semiconductor device comprising:

a central processing unit;
an interrupt control circuit;
and
a conversion portion that has a plurality of input channels including one or more first channels and one or more second channels, a channel selection portion for selecting one of the input channels, and analog-to-digital (A/D) convertor for converting a signal input from a selected input channel and outputting a selection signal to the channel selection portion and a completion signal,
wherein the conversion portion receives a scan conversion instruction from the central processing unit, sequentially selects a respective one of the input channels in accordance with a selection signal from the channel selection portion based on a specified selection order, and successively performs A/D conversion, and
wherein the interrupt control circuit outputs an interrupt signal to the central processing unit in response to A/D conversion completion notification received from the conversion portion when the conversion portion receives the scan conversion instruction and finishes A/D converting input signal input to all input channels.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/798,028Filed 13 Jul 2015 · continuation
Priority: JP 2010-28439321 Dec 2010
Published: US 2015/0317261 A15 Nov 2015
Granted: 15 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 13/102
Program control for peripheral devices: where the program performs an interfacing function, e.g. device driver
G06F 13/4221
On a parallel bus: being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
H03M 1/00
Analogue/digital conversion
H03M 1/12
Analogue/digital conversion; Digital/analogue conversion: analogue/digital converters

Family

Application13/331,923Parent of this continuation · filed 20 Dec 2011
US 2015/0317261 A1Pre-grant publication · published 5 Nov 2015
US 9,094,037 B2Parent of this continuation
US 2012/0159020 A1Published application
US 9,286,250 B2This patent

From the US filing history. Foreign family members aren’t listed.