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US 9,286,245 B2Granted
Hardware enforced memory access permissions
AssigneeIntel Corporation
InventorsDavid M. Durham, Ravi L. Sahita, Prashant Dewan
Life of this patent
Estimating the term…
Abstract
Embodiments of apparatuses and methods for hardware enforced memory access permissions are disclosed. In one embodiment, a processor includes address translation hardware and memory access hardware. The address translation hardware is to support translation of a first address, used by software to access a memory, to a second address, used by the processor to access the memory. The memory access hardware is to detect an access permission violation.
Claims12
A processor comprising:
- page walk hardware to traverse a hierarchy of page tables to perform an address translation of an actual linear address to a physical address, wherein the actual linear address is used by software to access a memory and the physical address is used by the processor to access the memory;
- a translation lookaside buffer to store a plurality of address translations performed by the page walk hardware;
- and
- memory access control hardware to look up, in a permissions map separate from the hierarchy of page tables, the physical address from the page walk hardware to find access permissions and an expected linear address, compare the expected linear address to the actual linear address, and store the address translation and the access permissions in the translation lookaside buffer only if the expected linear address matches the actual linear address.
1 more element
A method comprising:
- performing, by page walk hardware in a processor, an address translation of an actual linear address to a physical address by traversing a hierarchy of page tables, where the actual linear address is used by software to access a memory and the physical address is used by the processor to access a memory;
- and
- looking up, by memory access control hardware in the processor, the physical address in a permissions map separate from the hierarchy of page tables to find access permissions and an expected linear address;
- comparing, by the memory access control hardware in the processor, the expected linear address to the actual linear address;
- and
- storing the address translation and the access permissions in a translation lookaside buffer in the processor only if the expected linear address matches the actual linear address.
3 more elements
A system comprising:
- a memory;
- and
- a processor including
- page walk hardware to traverse a hierarchy of page tables to perform an address translation of an actual linear address to a physical address, wherein the actual linear address is used by software to access a memory and the physical address is used by the processor to access the memory;
- a translation lookaside buffer to store a plurality of address translations performed by the page walk hardware;
- and
- memory access control hardware to look up, in a permissions map separate from the hierarchy of page tables, the physical address from the page walk hardware to find access permissions and an expected linear address, compare the expected linear address to the actual linear address, and store the address translation and the access permissions in the translation lookaside buffer only if the expected linear address matches the actual linear address.
4 more elements
Dependencies are inferred from the claim text.