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US 9,286,229 B2Granted
Device to control updating of cache line
AssigneeRenesas Electronics Corporation
InventorIsao Kotera
Life of this patent
Estimating the term…
Abstract
A semiconductor device which can hold an instruction configuring a loop in a cache memory is provided. A main memory stores an instruction. A cache memory stores the instruction temporarily. A CPU reads an instruction from the main memory or the cache memory and executes the instruction. The cache control unit stops updating an instruction stored in the cache memory, when the same instruction as the instruction read in the past is again read within a prescribed number of read.
Claims20
A semiconductor device comprising:
- a main memory operable to store an instruction;
- a cache memory operable to store the instruction temporarily;
- a CPU (Central Processing Unit) operable to read an instruction from one of the main memory and the cache memory and operable to execute the instruction;
- and
- a cache control unit operable to stop updating of an instruction in the cache memory when the same instruction as the instruction read in the past is again read within a prescribed number of reads.
2 more elements
A semiconductor device comprising:
- a main memory operable to store an instruction;
- a cache memory operable to store the instruction temporarily;
- a controller operable to read an instruction from one of the main memory and the cache memory and operable to execute the instruction;
- and
- a cache control unit operable to control updating of an instruction in the cache memory when the same instruction as the instruction read in the past is again read within a prescribed number of reads.
2 more elements
Dependencies are inferred from the claim text.