Constraining prefetch requests to a processor socket
AssigneeIntel Corporation
InventorsSeth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban, Christopher B. Wilkerson, Shih-Lien L. Lu, Kingsum Chow
Life of this patent
Estimating the term…
Abstract
In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
Claims22
A processor comprising:
- at least one core including one or more execution units, a first cache memory and a first cache control logic, wherein the first cache control logic is to generate a first prefetch request to prefetch first data, wherein the first prefetch request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory, based on a first indicator of the first prefetch request to indicate that the first prefetch request is to be handled in a single level of a cache memory hierarchy.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- generating, in a first cache controller associated with a first cache memory of a cache memory hierarchy of a processor, a limited prefetch request to request first data, based on comparison of a result of a calculation to generate the limited prefetch request to a confidence metric;
- determining if the first data is present in a second cache memory of the cache memory hierarchy;
- and
- if so, promoting the first data to the first cache memory, and otherwise constraining the limited prefetch request to the processor.
A system comprising:
- a processor including a first core having a first cache memory and a second cache memory, and a first prefetcher associated with the first cache memory to issue a first prefetch request for first data to a memory hierarchy, the first prefetch request having a second indicator having a first state to identify a first prefetch type, and to issue a second prefetch request for second data to the second cache memory, the second prefetch request having a second indicator having a second state to identify a second prefetch type, wherein the second cache memory is to provide the second data to the first cache memory if present therein, and otherwise to abort the second prefetch request, based on the second indicator having the second state;
- and
- a memory coupled to the processor, the memory part of the memory hierarchy and comprising a dynamic random access memory (DRAM).
Dependencies are inferred from the claim text.