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US 9,286,222 B2Granted
Data processing apparatus and method for transferring workload between source and destination processing circuitry
AssigneeArm Limited
InventorPeter Richard Greenhalgh
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Abstract
In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.
Claims31
A data processing apparatus comprising:
- first processing circuitry and second processing circuitry, where both circuitries are configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time;
- power control circuitry for independently controlling power supply to the first processing circuitry and the second processing circuitry;
- a workload transfer controller configured to be responsive to a transfer stimulus to initiate a transfer of performance of the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing circuitry being placed in a power saving condition by the power control circuitry, the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry;
- wherein:
- at least the source processing circuitry has a cache;
- the power control circuitry is configured, following said transfer, to maintain at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry;
- cache snooping circuitry is configured, during the snooping period, to snoop data values in the cache of the source processing circuitry and to retrieve the snooped data values for the destination processing circuitry;
- and
- the power control circuitry is configured to place said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period, the power saving condition is a condition in which the cache of the source processing circuitry is not accessed by the cache snooping circuitry,
- wherein the snooping period ends on the occurrence of any one of a plurality of predefined snoop stop events, and
- wherein the any one of the plurality of predefined snoop stop events is based on at least one of:
- (i) a number of snoops performed by the cache snooping circuitry, (ii) a predetermined number of processing transactions of a predetermined type following said transfer, (iii) a predetermined number of processing cycles after the destination processing circuitry starts performing the transferred processing workload, (iv) a particular memory region of a shared memory is accessed for the first time by the destination processing circuitry after starting performance of the transferred processing workload, (v) a particular memory region of the shared memory, which was accessed by the destination processing circuitry for an initial period after starting performance of the transferred processing workload, is not accessed by the destination processing circuitry for a predetermined period, and (vi) the destination processing circuitry writing to a predetermined memory location of the shared memory for the first time after starting performance of the transferred processing workload.
9 more elements
A data processing apparatus comprising:
- first processing means for performing processing and second processing means for performing processing, the first processing means and second processing means are configured to perform a processing workload such that the processing workload is performed by one of the first processing means and the second processing means at a time;
- power control means for independently controlling power supply to the first processing means and the second processing means;
- workload transfer control means, responsive to a transfer stimulus, for initiating a transfer of performance of the processing workload from a source processing means to a destination processing means prior to the source processing means being placed in a power saving condition by the power control means, the source processing means being one of the first and second processing means and the destination processing means being the other of the first and second processing means;
- wherein:
- at least the source processing means has a cache means for storing cached data values;
- the power control means is configured, following said transfer, to maintain at least the cache means of the source processing means in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing means;
- cache snooping means is to snoop data values in the cache means of the source processing means during the snooping period, and retrieving the snooped data values for the destination processing means;
- and
- the power control means is configured to place said at least the cache means of the source processing means in the power saving condition following the end of the snooping period, the power saving condition is a condition in which the cache of the source processing means is not accessed by the cache snooping means,
- wherein the snooping period ends on the occurrence of any one of a plurality of predefined snoop stop events, and
- wherein the any one of the plurality of predefined snoop stop events is based on at least one of:
- (i) a number of snoops performed by the cache snooping means, (ii) a predetermined number of processing transactions of a predetermined type following said transfer, (iii) a predetermined number of processing cycles after the destination processing means starts performing the transferred processing workload, (iv) a particular memory region of a shared memory is accessed for the first time by the destination processing means after starting performance of the transferred processing workload, (v) a particular memory region of the shared memory, which was accessed by the destination processing means for an initial period after starting performance of the transferred processing workload, is not accessed by the destination processing means for a predetermined period, and (vi) the destination processing means writing to a predetermined memory location of the shared memory for the first time after starting performance of the transferred processing workload.
9 more elements
A data processing method for an apparatus comprising first processing circuitry and second processing circuitry configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time;
- the method comprising the steps of:
- performing the processing workload with a source processing circuitry, the source processing circuitry being one of the first and second processing circuitry and comprising a cache, the other of the first and second processing circuitry being a destination processing circuitry;
- in response to a transfer stimulus, transferring performance of the processing workload from the source processing circuitry to the destination processing circuitry prior to the source processing circuitry being placed in a power saving condition;
- following said transferring step, maintaining at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry;
- during the snooping period, employing cache snooping circuitry to snoop data values in the cache of the source processing circuitry and to retrieve the snooped data values for the destination processing circuitry;
- and
- placing said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period, the power saving condition is a condition in which the cache of the source processing circuitry is not accessed by the cache snooping circuitry,
- wherein the snooping period ends on the occurrence of any one of a plurality of predefined snoop stop events, and
- wherein the any one of the plurality of predefined snoop stop events is based on at least one of:
- (i) a number of snoops performed by the cache snooping circuitry, (ii) a predetermined number of processing transactions of a predetermined type following said transfer, (iii) a predetermined number of processing cycles after the destination processing circuitry starts performing the transferred processing workload, (iv) a particular memory region of a shared memory is accessed for the first time by the destination processing circuitry after starting performance of the transferred processing workload, (v) a particular memory region of the shared memory, which was accessed by the destination processing circuitry for an initial period after starting performance of the transferred processing workload, is not accessed by the destination processing circuitry for a predetermined period, and (vi) the destination processing circuitry writing to a predetermined memory location of the shared memory for the first time after starting performance of the transferred processing workload.
7 more elements
Dependencies are inferred from the claim text.