Back to results
US 9,286,210 B2Granted
System executes wear-leveling among flash memory modules
AssigneeHitachi, Ltd.
InventorsKatsuya Tanaka, Kentaro Shimada
Life of this patent
Estimating the term…
Abstract
A system including flash memory modules and a system controller. Each flash memory module includes flash memory chips and a memory controller to manage a plurality of blocks in the plurality of flash memory chips. The blocks are units for erasing data stored in the flash memory chips. The system controller performs wear leveling by exchanging data between a first flash memory module and a second flash memory module of the flash memory modules.
Claims25
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules including a plurality of flash memory chips and a memory controller configured to manage a plurality of blocks in the plurality of flash memory chips, where each of the plurality of blocks is a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to perform wear leveling between a first flash memory module and a second flash memory module included in the plurality of flash memory modules according to a first amount of writes directed to the first flash memory module and a second amount of writes directed to the second flash memory module so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules including a plurality of flash memory chips and a memory controller configured to manage a plurality of blocks in the plurality of flash memory chips, where each of the plurality of blocks is a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to perform wear leveling by transferring data from a first flash memory module to a second flash memory module, where each of the first flash memory module and the second flash memory module are included in the plurality of flash memory modules so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules includes a plurality of flash memory chips including a plurality of blocks, each of the plurality of blocks being a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to perform wear leveling between a first flash memory module and a second flash memory module included in the plurality of flash memory modules according to a first amount of writes directed to the first flash memory module and a second amount of writes directed to the second flash memory module so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules including a plurality of flash memory chips having a plurality of blocks, each of the plurality of blocks being a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to perform wear leveling by transferring data from a first flash memory module to a second flash memory module, and each of the first flash memory module and the second flash memory module are included in the plurality of flash memory modules so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules includes a plurality of flash memory chips and a memory controller which is configured to manage a plurality of blocks in the plurality of flash memory chips, each of the plurality of blocks being a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to select a flash memory module of the plurality of flash memory modules to write data according to an amount of writes directed to each of the plurality of flash memory modules so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
A system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules includes a plurality of flash memory chips including a plurality of blocks, each of the plurality of blocks being a unit for erasing data stored in the plurality of flash memory chips;
- and
- a system controller, which is coupled to the plurality of flash memory modules, and configured to select a flash memory module of the plurality of flash memory modules to write data according to an amount of writes directed to each of the plurality of flash memory modules so that erase counts of the plurality of blocks are leveled among the plurality of flash memory modules.
Dependencies are inferred from the claim text.