Apparatus and method for phase change memory drift management

A computer-implemented method comprising:

• detecting a write operation directed to a first block of a phase change memory;
• generating an entry in a first table to indicate the write operation;
• determining whether the first block has been refreshed following a power up condition;
• responsively generating a demand refresh signal to refresh the first block if the first block has not been refreshed following the power up condition;
• and
• performing the write operation after the demanded refresh.

Apparatus, comprising:

• a semiconductor chip comprising:
• a) refresh engine circuitry to:
• (i) control a power-up refresh of different blocks of a phase change memory after a power up event;
• (ii) detect that a write operation is targeted for a portion of the phase change memory prior to the portion having received a power-up refresh after the power up event and cause a special power-up refresh to be performed on the portion in direct response thereto, the portion being smaller than a size of a block;
• and,
• b) circuitry to perform a read of the portion at a demarcation voltage after the write operation has been performed at the portion.

An apparatus, comprising:

• a semiconductor chip comprising:
• memory controller circuitry to:
• (i) control a power-up refresh of different blocks of a phase change memory after a power up event;
• (ii) detect that a write operation is targeted for a portion of the phase change memory;
• iii) perform a read of the portion at a demarcation voltage after the write operation has been performed at the portion wherein the demarcation voltage is a first voltage if the read occurs within a pre-determined time period after the write operation or a second voltage if the read occurs after the pre-determined period after the write operation.