Apparatus for capturing results of memory testing

A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory, the method comprising:

• a computer extracting, from a first data file the names of a) a memory built in self test instance, b) a memory built in self test port name, and c) a name of a first memory, wherein the first data file controls the architectural arrangement of components of an integrated circuit, wherein the first data file describes an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of at least a part of an integrated circuit design;
• and
• the computer adding the extracted names into a description file that describes JTAG capture-shift test data registers such that the description file is configured to interpret a test result of a memory,
• wherein, in the description file, an appearance of the names of the memory built in self test instance, the memory built in self test port name for each memory built in self test instance port to be observed during a memory test, and corresponding memory instance to be tested during the memory test names matches an order of a plurality of test data registers included in the organization file, and
• wherein the memory is included in an integrated circuit structure that is configured for testing integrated circuit memory using the description file of Joint Test Action Group (JTAG) capture-shift test data registers.

A method of testing a first memory using the integrated circuit structure for testing integrated circuit memory, the method comprising:

• a computer generating, on an integrated circuit, an integrated circuit structure for testing integrated circuit memory, wherein the architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of the integrated circuit structure is based on a first data file that controls the architectural arrangement of components of at least a part of an integrated circuit design;
• the computer executing a test of an integrated circuit memory using the simulated integrated circuit structure for testing integrated circuit memory;
• the computer generating a result of the test;
• and
• the computer analyzing the result of the test using a description file of Joint Test Action Group (JTAG) capture-shift test data registers, wherein the description file is based, at least in part, on the first data file and describes a) the memory built in self test instance, b) the memory built in self test port name for each memory built in self test instance port to be observed during a memory test, and c) the name of each corresponding memory instance to be tested during the memory test,
• wherein, in the description file, an appearance of the names of the memory built in self test instance, the memory built in self test port name for each memory built in self test instance port to be observed during a memory test, and corresponding memory instance to be tested during the memory test names matches an order of a plurality of test data registers included in the organization file.