Fault-aware mapping for shared last level cache (LLC)
AssigneeIntel Corporation
InventorsTanausu Ramirez, Javier Carretero Casado, Enric Herrero, Matteo Monchiero, Xavier Vera
Life of this patent
Estimating the term…
Abstract
Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.
Claims24
An apparatus comprising:
- a cache having a plurality of cache lines;
- at least one central processing unit (CPU) core coupled to the cache;
- and
- a graphics processing unit (GPU) coupled to the cache, wherein the GPU, and not the CPU, is allowed to access a faulty cache line in the cache and wherein a faulty cache line is a cache line that has an amount of erroneous memory locations that cannot be written or read correctly, while the rest of the cache line is functioning correctly.
A method for utilizing a faulty cache line in a cache, the method comprising:
- determining, by a cache controller, that a source of a first cache access request is from a graphics processing unit (GPU);
- and
- allowing the GPU to access the cache according to the first cache access request even if the first cache access request is requesting access to the faulty cache line, wherein a faulty cache line is a cache line that has an amount of erroneous memory locations that cannot be written or read correctly, while the rest of the cache line is functioning correctly.
A method for utilizing a faulty cache line in a cache, the method comprising:
- detecting, by a cache controller, a cache miss event;
- determining that the faulty cache line is selected for eviction based on a cache replacement policy, wherein a faulty cache line is a cache line that has an amount of erroneous memory locations that cannot be written or read correctly, while the rest of the cache line is functioning correctly;
- and
- evicting the faulty cache line if the cache miss event resulted from a cache access by a graphics processing unit (GPU).
A method for reducing a power consumption of a microprocessor, the method comprising:
- lowering a supply voltage to the microprocessor to cause one or more cache lines in a cache to become faulty, wherein a faulty cache line is a cache line that has an amount of erroneous memory locations that cannot be written or read correctly, while the rest of the cache line is functioning correctly;
- identifying which of the cache lines are faulty cache lines;
- and
- for each cache access request to one of the faulty cache lines:
- allowing the cache access request to proceed if the cache access request is from a graphics processing unit (GPU) of the microprocessor, but not a central processing unit (CPU) core;
- and
- remapping the cache access request to access a fault-free cache line if the cache access request is from a CPU core of the microprocessor.
Dependencies are inferred from the claim text.