System and method for phase change memory with erase flag cells
AssigneeSTMicroelectronics S.r.l.
InventorsBharathManoj Manda, Abhishek Lal, Marco Pasotti, Marcella Carissimi
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Abstract
According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.
Claims34
A memory array comprising:
- a plurality of memory cells arranged in groups, each memory cell comprising a phase change memory cell;
- a plurality of erase flag cells, wherein each erase flag cell of the plurality of erase flag cells is associated with a group of the memory cells and indicates whether the group of the memory cells is to be treated as valid or erased;
- and
- a memory control circuit configured to set an erase flag cell to an erased value during an erase operation on the group of the memory cells associated with the erase flag cell without modifying the plurality of memory cells of the group of the memory cells associated with the erase flag cell.
A memory array comprising:
- a plurality of memory cells arranged in groups, each memory cell comprising a phase change memory cell;
- a plurality of erase flag cells, wherein
- each erase flag cell of the plurality of erase flag cells is associated with a group of the memory cells and indicates whether the group of the memory cells is to be treated as valid or erased,
- each group of memory cells comprises a memory word, and
- each memory word is separate from the erase flag cell associated therewith;
- and
- error code correction (ECC) memory cells formed in the memory array, wherein each erase flag cell has two dedicated ECC memory cells.
A memory circuit comprising:
- an array of non-volatile memory cells arranged in rows and columns, wherein the memory cells comprise a plurality of memory bits and a plurality of erase flags;
- a column decoder coupled to the array and configured to select a column from the columns in the array;
- a row decoder coupled to the memory array and configured to select a row from the rows in the array;
- and
- memory control circuitry configured to:
- receive a memory address and control signals,
- provide a column address to the column decoder, the column address based on the memory address,
- provide a row address to the row decoder, the row address based on the memory address, and
- cause memory operations to be performed on the memory cells based on the control signals, the memory operations comprising an erase operation that includes modifying a first erase flag associated with a first group of the plurality of memory bits, wherein the first erase flag is modified to indicate that the first group of the plurality of memory bits has been erased, and wherein the plurality of memory bits of the first group of the plurality of memory bits are not modified during the erase operation.
A method of operating a memory circuit comprising a plurality of memory cells and a plurality of flag cells, wherein the memory cells are partitioned into a plurality of groups of memory cells and each group of memory cells has an associated flag cell, wherein the method comprises:
- receiving an erase instruction associated with a first group of the memory cells;
- and
- modifying a first flag cell associated with the first group of the memory cells in response to the erase instruction, the first flag cell modified to indicate that the first group of the memory cells has been erased, wherein the plurality of memory cells of the first group of the memory cells are not modified in response to the erase instruction.
An integrated circuit memory device comprising:
- a plurality of memory cells formed on a substrate;
- a plurality of flag cells formed on the substrate, wherein each flag cell is associated with a group of the memory cells;
- and
- an integrated controller formed on the substrate, wherein the integrated controller is configured to set a flag cell to an erased value during an erase operation on a group of the memory cells associated with the flag cell without modifying the plurality of memory cells of the group.
Dependencies are inferred from the claim text.