Address detection circuit and memory including the same

A memory comprising:

• first to N-th word lines each connected to one or more memory cells;
• an address detection unit having first to N-th address storage units suitable for sequentially storing an input address in the address storage units during an active operation, generating first to N-th calculated values by performing a counting operation when an address is stored in the address storage units or the stored address is inputted, and storing an input address in a selected address storage unit when all of the address storage units each store an address, and detecting an address, which is inputted a reference number of times or more based on the calculated values;
• and
• a control unit suitable for sequentially refreshing the word lines in response to a refresh command inputted at a set period, and refreshing one or more word lines adjacent to a word line corresponding to an address detected by the address detection unit in response to the refresh command, when the address is detected by the address detection unit.