Hardware-assisted interthread push communication

A data processing system, comprising:

• a plurality of processor cores;
• one or more memories coupled to the plurality of processor cores;
• an interconnect fabric coupled to the plurality of processor cores;
• a switch coupled to the interconnect fabric, wherein the switch includes a data structure having a plurality of entries, and wherein the switch, responsive to receiving, from the interconnect fabric, a request to push a message referenced by an instruction of a sending thread executing on one of the plurality of processor cores to a receiving thread, determines whether the sending thread is authorized to push the message to the receiving thread, at least in part, by attempting to access an entry of a data structure utilizing a key derived from at least one identifier of the sending thread, and wherein the switch, responsive to access to the entry being successful, utilizes content of the entry to determine an address of a mailbox of the receiving thread and to push the message to the mailbox of the receiving thread, and wherein the switch, responsive to access to the entry not being successful, refrains from pushing the message to the mailbox of the receiving thread.