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US 9,286,128 B2Granted
Processor scheduling with thread performance estimation on cores of different types
AssigneeIntel Corporation
InventorsAamer Jaleel, Kenzo Van Craeynest, Paolo Narvaez, Joel Emer
Life of this patent
Estimating the term…
Abstract
A processor is described having an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread. The processor also includes statistics collection circuitry to support calculation of the following: the first thread's performance on the out-of-order core; an estimate of the first thread's performance on the non-out-of-order core; the second thread's performance on the non-out-of-order core; an estimate of the second thread's performance on the out-of-order core.
Claims20
A processor comprising:
- an out-of-order core to execute a first thread;
- a non-out-of-order core to execute a second thread;
- statistics collection circuitry to support calculation of the following:
- said first thread's performance on said out-of-order core;
- an estimate by the out-of-order core of said first thread's performance on said non-out-of-order core;
- said second thread's performance on said non-out-of-order core;
- and
- an estimate by the non-out-of-order core of said second thread's performance on said out-of-order core;
- and
- circuitry to switch the first thread to the non-out-of-order core and switch the second thread to the out-of-order core to speed up the second thread, wherein said statistics collection circuitry is to track a number of instructions between a later instruction having a dependency on an earlier instruction.
7 more elements
A method comprising:
- executing a first thread on an out-of-order core;
- executing a second thread on a non-out-of-order core;
- tracking statistics of the first and second threads to support calculation of the following:
- said first thread's performance on said out-of-order core;
- an estimate by the out-of-order core of said first thread's performance on said non-out-of-order core;
- said second thread's performance on said non-out-of-order core;
- and
- an estimate by the non-out-of-order core of said second thread's performance on said out-of-order core;
- tracking a number of instructions between a later instruction having a dependency on an earlier instruction;
- and
- switching the first thread to the non-out-of-order core and switching the second thread to the out-of-order core to speed up the second thread.
8 more elements
A computing system comprising:
- a processor comprising an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread;
- statistics collection circuitry to track a number of instructions between a later instruction having a dependency on an earlier instruction;
- and
- thread scheduling intelligence to switch said first thread to said non-out-of-order core and switch said second thread to said out-of-order core in light of:
- said first thread's performance on said out-of-order core;
- an estimate by the out-of-order core of said first thread's performance on said non-out-of-order core;
- said second thread's performance on said non-out-of-order core;
- and
- an estimate by the non-out-of-order core of said second thread's performance on said out-of-order core.
6 more elements
Dependencies are inferred from the claim text.