Accessing time stamps during transactions in a processor
AssigneeAdvanced Micro Devices, Inc.
InventorsMartin T. Pohlack, Stephan Diestelhorst
Life of this patent
Estimating the term…
Abstract
The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.
Claims18
A method for handling operations during a transaction in a processor, wherein one or more attempts are made to acquire timestamps during the transaction, the method comprising:
- monitoring acquisition of time stamps during the transaction, wherein each time stamp is acquired from a time stamp counter in the processor based on executing a corresponding time-stamp acquisition instruction;
- and
- preventing acquisition of a time stamp that meets a predetermined condition, the time stamp meeting the predetermined condition when the time stamp can be used to determine that one or more transactions executed concurrently, wherein the preventing comprises aborting the transaction or at least one other concurrent transaction when one or more time stamps and one or more operations in the transaction or the at least one other concurrent transaction make apparent an inconsistent ordering between the transaction and the at least one other concurrent transaction.
A core comprising one or more circuits for executing instructions, the core handling operations during a transaction, wherein one or more attempts are made to acquire timestamps during the transaction, wherein the core is configured to:
- monitor acquisition of time stamps during the transaction, wherein each time stamp is acquired from a time stamp counter based on executing a corresponding time-stamp acquisition instruction;
- and
- prevent acquisition of a time stamp that meets a predetermined condition, the time stamp meeting the predetermined condition when the time stamp can be used to determine that one or more transactions executed concurrently, wherein the preventing comprises aborting the transaction or at least one other concurrent transaction when one or more time stamps and one or more operations in the transaction or the at least one other concurrent transaction make apparent an inconsistent ordering between the transaction and the at least one other concurrent transaction.
A processor that handles operations during a transaction, wherein one or more attempts are made to acquire timestamps during the transaction, comprising:
- one or more cores;
- a time stamp counter;
- and
- a memory coupled to the one or more cores, wherein the memory is configured to store instructions and data for the one or more cores;
- wherein at least one core is configured to:
- monitor acquisition of time stamps during the transaction, wherein each time stamp is acquired from the time stamp counter based on executing a corresponding time-stamp acquisition instruction;
- and
- prevent acquisition of a time stamp that meets a predetermined condition, the time stamp meeting the predetermined condition when the time stamp can be used to determine that one or more transactions executed concurrently, wherein the preventing comprises aborting the transaction or at least one other concurrent transaction when one or more time stamps and one or more operations in the transaction or the at least one other concurrent transaction make apparent an inconsistent ordering between the transaction and the at least one other concurrent transaction.
Dependencies are inferred from the claim text.