Using register last use infomation to perform decode-time computer instruction optimization
AssigneeInternational Business Machines Corporation
InventorsMichael K. Gschwind, Valentina Salapura
Life of this patent
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Abstract
Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified as a last-use register, where a last-use register has a value that is not to be accessed by later instructions, whereby the two computer machine instructions are replaced by a single optimized internal instruction for execution, the single optimized instruction not including the last-use register.
Claims8
A computer implemented method for optimizing instructions to be executed, the method comprising:
- fetching two instructions for execution;
- determining, by a processor, that the two instructions to be executed are candidates for optimization to a single optimized internal instruction, the two instructions comprising a first instruction identifying a first operand as a target operand and a second instruction identifying the first operand as a source operand, the first instruction preceding the second instruction in program order;
- determining that the first operand is specified as a last-use operand;
- creating, by the processor, the single optimized internal instruction based on the two instructions, wherein the single optimized internal instruction does not specify the first operand;
- and
- executing the single optimized internal instruction instead of the two instructions.
Dependencies are inferred from the claim text.