Efficient usage of a multi-level register file utilizing a register file bypass

A method comprising:

• determining that a logical register has been selected for unmapping from a physical register in a first level register file, wherein data in the physical register in the first level register file is moved to a physical register in a second level register file;
• determining that an instruction in an issue queue indicates the logical register;
• loading the data into a first of a set of one or more storage locations designated for bypassing register mapping;
• and
• selecting the first of the set of one or more storage locations as input to an execution unit that will execute the instruction, wherein the execution unit executes the instruction with the data while bypassing register mapping of the logical register.

A computer program product for bypassing a first level register file, the computer program product comprising:

• a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code configured to:
• determine that a logical register has been selected for unmapping from a physical register in a first level register file, wherein data in the physical register in the first level register file is moved to a physical register in a second level register file;
• determine that an instruction in an issue queue indicates the logical register;
• load the data into a first of a set of one or more storage locations designated for bypassing register mapping;
• and
• select the first of the set of one or more storage locations as input to an execution unit that will execute the instruction, wherein the execution unit executes the instruction with the data while bypassing register mapping of the logical register.

A processor comprising:

• an execution unit;
• a first level register file of first physical registers;
• a second level register file of second physical registers, wherein the first level register file is more efficiently accessible relative to the second level register file;
• a plurality of storage locations designated to host data associated with a plurality of logical registers that will bypass register mapping;
• and
• a register file bypass controller coupled with the execution unit and the second level register file, the register file bypass controller operable to determine an instruction that indicates a first logical register unmapped from one of the first physical registers in the first level register file before the instruction issues, to load data of a corresponding logical register into one of the plurality of storage locations, and to select one of the plurality of storage locations as input to the execution unit for execution of the instruction while avoiding mapping the corresponding logical register to the one of the first physical registers in the first level register file.