Method and apparatus for a hierarchical synchronization barrier in a multi-node system

An apparatus for a hierarchical barrier synchronization of cores and nodes on a multiprocessor system, comprising:

• a plurality of cores arranged in an integrated circuit;
• a status bit register and a mask bit register associated with a core, for each of the plurality of cores;
• the status bit register operable to store input bit signals received from each of said plurality of cores;
• a control logic circuit operable to perform a Boolean “AND” function on the input bit signal and a mask signal stored in the mask bit register associated with a core to produce a first output for each of the plurality of cores, and perform a Boolean “OR” function on an inverted mask signal associated with the core and the first output to produce a second output for each of the plurality of cores,
• the control logic circuit further operable to perform a Boolean “AND” function on the second outputs associated with the plurality of cores to determine whether said plurality of cores participating in synchronization process all reached barrier,
• the control logic circuit further operable to determine whether only on-chip synchronization is needed or whether inter-node synchronization is needed, and in response to determining that all of the plurality of cores on the integrated circuit participating in the synchronization process reached the barrier, notifying the plurality of cores on the chip if it is determined that only on-chip synchronization is needed, and after all of the plurality of cores on the integrated circuit participating in the synchronization process reached the barrier, communicating the synchronization signal to outside of the integrated circuit if it is determined that inter-node synchronization is needed.