Predicting future power level states for processor cores

An apparatus comprising:

• a multicore processor including a plurality of cores;
• a predictor coupled to the multicore processor to predict a distribution of operation states for the plurality of cores during a next utilization cycle, based on power state change information for the plurality of cores during a current utilization cycle;
• and
• logic to receive the distribution and to determine a low power state for at least one core of the plurality of cores for the next utilization cycle, wherein the logic is to cause the at least one core to enter into the low power state if it is a lower power state than an operating system (OS) low power state when the at least one core is to idle during the next utilization cycle.

An article comprising a non-transitory machine-accessible storage medium including instructions stored in the non-transitory machine-accessible storage medium that when executed by a processor of a system cause the system to:

• generate, in a predictor of the processor, prediction information including a prediction of an idle-busy pattern of the processor including a plurality of cores for a next operating period based on power state change information of the plurality of cores during a first operating period;
• determine, in a selector of the processor, a low power state for the plurality of the cores of the processor for the next operating period based at least in part on the idle-busy pattern;
• and
• cause, via a logic of the processor, a core to enter into the determined low power state corresponding to a lower of the low power state or an operating system (OS) low power state when the core is to idle during the next operating period.