Memory system with improved bus timing calibration
AssigneeApple Inc.
InventorsRoni Shoev, Yoav Kasorla
Life of this patent
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Abstract
A method includes communicating between a memory controller and multiple memory devices over an interface that includes at least a control signal and an information signal. For each memory device, a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, is produced. The respective individual skew parameter is stored coupled to each memory device. The timing misalignment is corrected at the memory device using the stored individual timing skew.
Claims18
A method, comprising:
- communicating between a memory controller and multiple memory devices over an interface that comprises at least a control signal and an information signal;
- for each memory device, producing a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device;
- and
- storing the respective individual skew parameter coupled to each memory device, and correcting the timing misalignment at the memory device using the stored individual timing skew.
An apparatus, comprising:
- multiple memory devices;
- and
- a memory controller, which is configured to communicate with the multiple memory devices over an interface that comprises at least a control signal and an information signal, to produce, for each memory device, a respective individual skew parameter that is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, to provide the respective individual skew parameter for storage coupled to each memory device, and to cause each memory device to correct the timing misalignment using the stored individual timing skew.
Dependencies are inferred from the claim text.