Deterministic clock crossing

A tablet computing device comprising:

• a touch screen interface;
• a reset circuit on a first die to generate a forwarded FIFO reset signal;
• a clock generation circuit on the first die to generate a reference clock signal;
• control circuitry on the first die to generate a forwarded signal which identifies a window based on the reference clock signal;
• a phase locked loop (PLL) on a second die coupled to receive the reference clock signal;
• and
• a FIFO on the second die to be reset within the window identified by the forwarded signal.

A system comprising:

• an onmidirectinal antenna;
• a reset circuit on a first die to generate a forwarded FIFO reset signal;
• a clock generation circuit on the first die to generate a reference clock signal;
• control circuitry on the first die to generate a forwarded signal which identifies a window based on the reference clock signal;
• a phase locked loop (PLL) on a second die coupled to receive the reference clock signal;
• and
• a FIFO on the second die to be reset within the window identified by the forwarded signal.

An apparatus, comprising:

• a first semiconductor chip, comprising:
• a) reset signal generation logic circuitry to generate a reset signal, said reset signal to be forwarded to a second semiconductor chip to reset a FIFO of the second semiconductor chip that is coupled to the first semiconductor chip;
• b) a first phase lock loop circuit to generate a reference clock that is to be received by a second phase lock loop circuit of the second semiconductor chip, the second phase lock loop circuit to clock the FIFO of the second semiconductor chip;
• c) sideband signal circuitry to generate sideband information to be received by the second semiconductor chip to establish a window based on the reference clock at which a reset of the FIFO buffer is to take place.