US 9,285,824 B2 · Systems and methods for DQS gating

Abstract

Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.

Claims26

Dependent claims

A system for timing read operations in which a memory controller sends a read request to a memory device and receives, from the memory device, data and a timing signal, and in which the timing signal includes a series of timing pulses that include a first timing pulse and a last timing pulse, the system comprising:

a timing control circuit configured to, in response to the read request, generate a control signal pulse that has (i) a leading edge at a predetermined delay past receipt of the read request and (ii) a trailing edge at a trailing edge of the first timing pulse;
a gating circuit configured to pass the timing signal to the memory controller only during a gating window and to generate the gating window by:
opening the gating window during the control signal pulse, and
closing the gating window upon lapse of a predetermined delay after a trailing edge of the last timing pulse, the last timing pulse being determined based on a counter that is triggered to begin counting by the control signal pulse.

1 more element

A method for timing read operations in which a memory controller sends a read request to a memory device and receives, from the memory device, data and a timing signal, and in which the timing signal includes a series of timing pulses including a first timing pulse and a last timing pulse, the method comprising:

generating, in response to the read request, a control signal pulse that has (i) a leading edge at a predetermined delay past receipt of the read request and (ii) a trailing edge at a trailing edge of the first timing pulse;
passing the timing signal to the memory controller only during a gating window;
and
generating the gating window by:
opening the gating window during the control signal pulse, and
closing the gating window upon lapse of a predetermined delay after a trailing edge of the last timing pulse, the last timing pulse being determined based on a counter that is triggered to begin counting by the control signal pulse.

3 more elements

Dependencies are inferred from the claim text.

Systems and methods for DQS gating

Life of this patent

Systems and methods for DQS gating

Life of this patent

Abstract

Claims26