Ultra-low noise voltage reference circuit
AssigneeAnalog Devices, Inc.
InventorsArthur J. Kalb, John Sawa Shafran
Life of this patent
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Abstract
A voltage reference circuit comprises a plurality of ΔVBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ΔVBE voltage. The plurality of ΔVBE cells are stacked such that their ΔVBE voltages are summed. A last stage is coupled to the summed ΔVBE voltages and arranged to generate one or more VBE voltages which are summed with the ΔVBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ΔVBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.
Claims29
A voltage reference circuit, comprising:
- a plurality of ΔVBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ΔVBE voltage, said plurality of ΔVBE cells stacked such that their ΔVBE voltages are summed;
- and
- a last stage which is coupled to said summed ΔVBE voltages, said last stage arranged to generate multiple VBE voltages which are summed with said summed ΔVBE voltages to provide a reference voltage.
A voltage reference circuit comprising:
- a first bipolar junction transistor (BJT) Q1 having a base terminal connected to a first node, an emitter terminal connected to a circuit common point, and collector terminal connected to a second node;
- a second bipolar junction transistor (BJT) Q2 having a base terminal connected to said second node, an emitter terminal connected to a third node, and collector terminal connected to said first node;
- a third bipolar junction transistor (BJT) Q3 having a base terminal connected to a fourth node, an emitter terminal connected to said second node, and collector terminal connected to a fifth node;
- a fourth bipolar junction transistor (BJT) Q4 having a base terminal connected to said fourth node, an emitter terminal connected to said first node, and collector terminal connected to a sixth node;
- and
- a field effect transistor (FET) connected between said third node and said circuit common point, wherein a voltage across said FET is a ΔVBE voltage.
A voltage reference circuit comprising:
- a first NMOS FET Q1 having a gate terminal connected to a first node, a source terminal connected to a circuit common point, and a drain terminal connected to a second node;
- a second NMOS FET Q2 having a gate terminal connected to said second node, a source terminal connected to a third node, and a drain terminal connected to said first node;
- a third NMOS FET Q3 having a gate terminal connected to a fourth node, a source terminal connected to said second node, and a drain terminal connected to a fifth node;
- a fourth NMOS FET Q4 having a gate terminal connected to said fourth node, a source terminal connected to said first node, and a drain terminal connected to a sixth node;
- and
- a FET connected between said third node and said circuit common point,
- wherein a voltage across said FET is proportional to absolute temperature.
Dependencies are inferred from the claim text.