Time to digital converter with successive approximation architecture

A time to digital converter comprising:

• a phase-frequency detection circuit having a pair of inputs respectively receiving first and second signals, said phase-frequency detection circuit generating both an up and a down control signal at corresponding outputs thereof, each of said up and down control signals having a pulse width and one of said up and down control signals having said pulse width thereof representing a time difference between receipt of leading edges of said first and second signals;
• a current switching unit having a pair of inputs coupled to said phase-frequency detection circuit for receiving said up and down control signals, said current switching unit generating an up current signal for a first time period corresponding to said pulse width of said up control signal and generating a down current signal for a second time period corresponding to said pulse width of said down control signal;
• and
• a successive approximation analog to digital converter having a capacitor digital to analog converter operatively coupled to said current switching unit for generating a respective voltage corresponding to each of said up and down current signals, said successive approximation analog to digital converter generating a digital representation of a difference between said voltages of said capacitor digital to analog converter to define said time difference between receipt leading edges of said first and second signals.

A method of converting a measured time period representing a time difference between receipt of leading edges of a pair of signals to a digital representation thereof, the method comprising:

• detecting a rising edge of each of said pair of signals and measuring a time difference therebetween;
• generating two control signals with each having a pulse width where a difference in pulse width between said two control signals is equivalent to said measured time difference;
• respectively redistributing charge in a pair of arrays of binary-weighted capacitors respectively responsive to said two control signals to establish corresponding voltages thereacross, a difference between the voltages across said pair of arrays of binary-weighted capacitors thereby being equivalent to said measured time difference;
• and
• successively comparing the voltages established across selected ones of said binary-weighted capacitors between said pair of arrays of binary-weighted capacitors and storing a result thereof in a register to generate in said register a digital representation of said measured time difference.