Managing chip testing data
AssigneeInternational Business Machines Corporation
InventorsSteven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
Life of this patent
Estimating the term…
Abstract
A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.
Claims15
A system comprising:
- a scan channel comprising a plurality of scannable latches, the scan channel configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip;
- an aperture configured to select at least one bit output during a scan out of the scan channel and further configured to mask other bits, the at least one bit corresponding to output from a subset of the plurality of scannable latches, the other bits corresponding to the plurality of scannable latches outside of the subset;
- and
- a storage configured to store the selected at least one bit unmodified and further configured to not store the masked other bits.
A method of testing a chip comprising:
- scanning input data into a scan channel, wherein the scan channel comprises a plurality of scannable latches, configured to input the input data to logic circuits on the chip and further configured to receive outputs from the logic circuits on the chip;
- selecting at least one bit from the plurality of scannable latches for storing during a scan out of the scan channel, the at least one bit corresponding to a subset of the plurality of scannable latches;
- scanning out of the scan channel;
- masking, by an aperture, bits corresponding to the plurality of scannable latches outside of the subset;
- and
- storing the at least one bit unmodified in a storage, without the masked bits, during the scan out of the scan channel.
A method of testing a chip by a tester comprising:
- scanning input data into a scan channel, wherein the scan channel comprises a plurality of scannable latches, configured to input the input data to logic circuits on the chip and further configured to receive outputs from the logic circuits on the chip;
- selecting at least one bit from the plurality of scannable latches for storing during a scan out of the scan channel, the at least one bit corresponding to a subset of the plurality of scannable latches;
- scanning out of the scan channel;
- masking, by an aperture, bits corresponding to the plurality of scannable latches outside of the subset;
- storing the selected unmodified bits in a storage, without the masked bits, during the scan out of the scan channel;
- and
- sending the selected bits unmodified from the storage to the tester at a tester speed.
Dependencies are inferred from the claim text.