Method and apparatus for characterizing thermal marginality in an integrated circuit
AssigneeQUALCOMM Incorporated
InventorsTapan J Chakraborty, Rajamani Sethuram, Ratibor Radojcic
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Abstract
Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
Claims47
A method for testing integrated circuit (IC) performance, comprising:
- generating, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the generating the one or more thermal hot spots in one or more core blocks comprises exciting at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block;
- and
- initiating one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present.
An apparatus for testing integrated circuit (IC) performance, comprising:
- means for generating, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the means for generating the one or more thermal hot spots in one or more core blocks is configured to excite at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block;
- and
- means for initiating one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present.
An apparatus for testing integrated circuit (IC) performance, comprising:
- at least one processor configured to:
- generate, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the at least one processor is configured to generate the one or more thermal hot spots in one or more core blocks by exciting at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block;
- and
- initiate one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present;
- and
- a memory coupled to the at least one processor.
A non-transitory computer-readable medium containing instructions comprising:
- code for generating, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the code generating the one or more thermal hot spots in one or more core blocks comprises code for exciting at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block;
- and
- code for initiating one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one or the one or more thermal hot spots is present.
Dependencies are inferred from the claim text.