Switching regulator cycle-by-cycle current estimation

A switching regulator, comprising:

• an output phase including a high-side transistor and a low-side transistor operable to switch on and off at different periods responsive to a pulse width modulation (PWM) signal applied to the output phase, each cycle of the PWM signal having an on-portion and an off-portion;
• a current sense circuit operable to sense the current of the low-side transistor;
• an analog-to-digital converter operable to sample the sensed low-side transistor current during the off-portion for each PWM cycle;
• and
• a current estimator operable to estimate a cycle average current for the present PWM cycle based on the low-side transistor current sampled during the off-portion for the immediately preceding PWM cycle and a pulse width estimate for the on-portion for the present PWM cycle, determine a prediction error by comparing the cycle average current estimated for each PWM cycle to a measured phase current for the same PWM cycle upon completion of that PWM cycle, and compensate for the prediction error so that a steady-state response of the switching regulator is unaffected by the prediction error.

A method of estimating cycle average current for a plurality of output phases of a multi-phase switching regulator during pulse width modulation (PWM) cycles of the multi-phase switching regulator, each PWM cycle having an on-portion and an off-portion, the method comprising:

• measuring a low-side transistor current of each output phase during the off-portion for each PWM cycle;
• estimating a pulse width for the on-portion for the present PWM cycle;
• estimating an average current of each output phase for the present PWM cycle based on the low-side transistor current measured for each output phase during the off-portion for the immediately preceding PWM cycle and the pulse width estimate for the on-portion for the present PWM cycle;
• combining the average current estimates for the plurality of output phases to generate a total average current estimate for the present PWM cycle;
• comparing the total average current estimated for each PWM cycle to a measured current for the same PWM cycle upon completion of that PWM cycle to generate a prediction error;
• and
• compensating for the prediction error so that a steady-state response of the multi-phase switching regulator is unaffected by the prediction error.

A multi-phase switching regulator, comprising:

• a plurality of output phases each including a high-side transistor and a low-side transistor operable to switch on and off at different periods responsive to a pulse width modulation (PWM) signal, each cycle of the PWM signal having an on-portion and an off-portion;
• a current sense circuit operable to sense the current of each low-side transistor;
• an analog-to-digital converter operable to sample the sensed low-side transistor current of each output phase during the off-portion for each PWM cycle;
• and
• a current estimator operable to estimate an average current of each output phase for the present PWM cycle based on the low-side transistor current measured for each output phase during the off-portion for the immediately preceding PWM cycle and a pulse width estimate for the on-portion for the present PWM cycle, combine the average current estimates for the plurality of output phases to generate a total average current estimate for the present PWM cycle, determine a prediction error by comparing the average current estimated for each PWM cycle to a measured current for the same PWM cycle upon completion of that PWM cycle, and compensate for the prediction error so that a steady-state response of the multi-phase switching regulator is unaffected by the prediction error.