Real-time resampling of optical coherence tomography signals using a field programmable gate array

A field programmable gate array (FPGA) comprising:

• a plurality of logic circuits interconnected to:
• receive a control signal;
• receive an incoming signal;
• extract normalized phase information from the received control signal;
• unwrap the extracted normalized phase information;
• multiply the unwrapped extracted normalized phase information with an interpolation factor to obtain recalculated phase information;
• determine one or more integer values within a range of phase values defined by the recalculated phase information;
• interpolate one or more values of the received incoming signal according to the identified one or more integer values;
• and
• output a sampled version of the received incoming signal according at least to the interpolated one or more values of the received incoming signal.

A method for processing a data signal, the method comprising:

• receiving, at a processing circuit, a control signal representative of an analog signal that has varying frequency in time;
• receiving, at the processing circuit, a data signal;
• determining, by the processing circuit, equally spaced points in phase of the received control signal, wherein each identified point in phase of the identified equally spaced points in phase corresponds to a respective pair of values of the received control signal;
• resampling, by processing circuit, the received data signal according to the identified equally spaced points in phase of the received control signal, said resampling comprising:
• for each identified point in phase, linearly interpolating, by the processing circuit a corresponding value of the received data signal between the respective pair of values of the received data signal corresponding to the identified point in phase;
• and
• outputting a sampled version of the received data signal according at least to the interpolated corresponding values of the received data signal.

A system comprising:

• a first input configured to receive a control signal;
• a second input configured to receive an incoming signal;
• a first logic circuit configured to extract phase information from the received control signal;
• a second logic circuit configured to obtain phase points from the extracted phase information;
• a third logic circuit configured to multiply each obtained phase point of the obtained phase points with an interpolation factor to obtain recalculated phase points;
• a fourth logic circuit configured to determine desired phase points within a range defined by the recalculated phase points, wherein each desired phase point of the desired phase points:
• is evenly divisible by a specified number;
• and
• has a value that falls between respective values of a corresponding pair of recalculated phase points within the range defined by the recalculated phase points;
• and
• a fifth logic circuit configured to resample the received incoming signal according to the identified desired phase points, and output a sampled version of the received incoming signal according to at least the resampled received incoming signal.