Apparatuses having a ferroelectric field-effect transistor memory array and related method

An apparatus, comprising:

• a first vertical ferroelectric field-effect transistor (FeFET) stack including a first plurality of gates separated from a first FET structure by a first ferroelectric material;
• and
• a second vertical FeFET stack including a second plurality of gates separated from a second FET structure by a second ferroelectric material, wherein:
• the first vertical FeFET stack and the second vertical FeFET stack are stacked horizontally and separated by a dielectric material;
• and
• the first ferroelectric material is shared by FeFETs of the first vertical FeFET stack and the second ferroelectric material is shared by FeFETs of the second vertical FeFET stack.

An apparatus, comprising:

• a three-dimensional memory array having a plurality of ferroelectric field-effect transistor (FeFET) memory cells located at intersections of ferroelectric material coupled with a plurality of bit lines and a plurality of word lines, wherein:
• the plurality of FeFET memory cells are located along vertical strings of the three-dimensional memory array;
• and
• the ferroelectric material is shared by the plurality of FeFET memory cells along the vertical strings.