Method and apparatus for error management of an integrated circuit system
AssigneeScaleo Chip
InventorBruno Sallé
Life of this patent
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Abstract
An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
Claims17
An Error Management Unit comprising:
- a circuit for collection of any of critical errors and non-critical errors;
- an error reaction module, the error reaction module configured to determine the necessary operation of the Error Management Unit responsive to collected any of critical errors and non-critical errors;
- a state machine for controlling the Error Management Unit, the state machine configured to operate in:
- a first state present when the Error Management Unit power is reset;
- a second state present when the Error Management Unit may be configured;
- a third state present when no errors are detected as occurring;
- a fourth state present when at least an unmasked non-critical error is signaled and timeout of the at least an unmasked non-critical error is enabled;
- and,
- a fifth state present when at least a critical error or at least an unmasked non-critical error is detected and the Error Management Unit applies an error reaction request to the error reaction module;
- and
- a configuration interface for receiving external configuration information for the Error Management Unit with respect to at least a reaction to the any of critical errors and non-critical errors and any combination thereof.
A method for error control by a state machine of an error management unit, the method comprising:
- causing the state machine to reach a first state responsive to a power reset of the Error Management Unit;
- causing the state machine to reach a second state responsive of a configuration signal for Error Management Unit configuration;
- causing the state machine to reach a third state responsive to detection of an occurrence of at least an error;
- causing the state machine to reach a fourth state responsive to at least an unmasked non-critical error of the at least an error is signaled and timeout of the at least an unmasked non-critical error is enabled;
- and
- causing the state machine to reach a fifth state responsive to at least a critical error of the at least an error or at least an unmasked non-critical error of the at least an error is detected responsive of the Error Management Unit asserting an error reaction request.
Dependencies are inferred from the claim text.