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US 9,268,528 B2Granted
System and method for dynamically reducing power consumption of floating-point logic
AssigneeNVIDIA Corporation
InventorsDavid C. Tannenbaum, Srinivasan Iyer
Life of this patent
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Abstract
A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output.
Claims20
A method, comprising:
- computing a first number of trailing zeros in a first significand associated with a floating-point format input operand;
- computing a second number of trailing zeros in a second significand;
- summing the first number of trailing zeros with the second number of trailing zeros to produce a trailing zero sum;
- receiving a disable control signal that is based on a characteristic of the floating-point format input operand and the trailing zero sum;
- disabling a portion of a logic circuit based on the disable control signal;
- and
- processing the first significand and the second significand by the logic circuit to generate an output.
4 more elements
A processing unit, comprising:
- a logic disable unit that is configured to:
- compute a first number of trailing zeros in a first significand associated with a floating-point format input operand;
- compute a second number of trailing zeros in a second significand;
- and
- sum the first number of trailing zeros with the second number of trailing zeros to produce a trailing zero sum;
- and
- arithmetic logic circuitry configured to:
- receive a disable control signal that is based on a characteristic of the floating-point format input operand and the trailing zero sum;
- disable a portion of the arithmetic logic circuitry based on the disable control signal;
- and
- process the first significand and the second significand to generate an output.
8 more elements
A system, comprising:
- a memory;
- and
- a processing unit, comprising:
- a logic disable unit that is configured to:
- compute a first number of trailing zeros in a first significand associated with a floating-point format input operand;
- compute a second number of trailing zeros in a second significand;
- and
- sum the first number of trailing zeros with the second number of trailing zeros to produce a trailing zero sum;
- and
- arithmetic logic circuitry configured to:
- receive a disable control signal that is based on a characteristic of the floating-point format input operand and the trailing zero sum;
- disable a portion of the arithmetic logic circuitry based on the disable control signal;
- and
- process the first significand and the second significand to generate an output.
11 more elements
Dependencies are inferred from the claim text.