Apparatus and methods for capacitive load reduction
AssigneeSkyworks Solutions, Inc.
InventorSabah Khesbak
Life of this patent
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Abstract
Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.
Claims20
A power amplifier system comprising:
- a first power amplifier configured to receive a power amplifier supply voltage, the first power amplifier having an enabled state and a disabled state;
- a supply control circuit configured to control a voltage level of the power amplifier supply voltage;
- a first switchable capacitor;
- a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage;
- and
- a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled to reduce a capacitive loading of the supply control circuit.
A mobile device comprising:
- a first power amplifier configured to receive a power amplifier supply voltage and an input signal, the first power amplifier having an enabled state and a disabled state;
- a transceiver configured to generate the input signal;
- a supply control circuit configured to control a voltage level of the power amplifier supply voltage;
- a first switchable capacitor;
- a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage;
- and
- a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled to reduce a capacitive loading of the supply control circuit.
A multi-chip module comprising:
- a first switchable capacitor;
- a power amplifier die including a first power amplifier configured to receive a power amplifier supply voltage, the first power amplifier having an enabled state and a disabled state, the power amplifier die further including a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage;
- and
- a bias control die including a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled.
Dependencies are inferred from the claim text.