US 9,257,414 B2Granted

Stacked semiconductor structure and method

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsSzu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung

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Abstract

A method for forming a stacked semiconductor structure comprises providing a first chip comprising a plurality of first active circuits and a first aluminum connection pad, depositing a first dielectric layer on a first side of the first chip, forming a first copper bonding pad on the first aluminum connection pad, providing a second chip comprising a plurality of second active circuits, depositing a second dielectric layer on a first side of the second chip, forming a second copper bonding pad in the second dielectric layer, stacking the first chip on the second chip, wherein the first copper bonding pad is in direct contact with the second copper bonding pad and bonding the first chip and the second chip to form a uniform bonded feature.

Claims20

Dependent claims

A method comprising:

providing a first chip comprising a plurality of first active circuits and a first connection pad formed of a first conductive material;
depositing a first dielectric layer over the first chip;
forming a first bonding pad on the first connection pad, wherein:
the first bonding pad is in direct contact with the first connection pad;
and
the first bonding pad is formed of a second conductive material;
providing a second chip comprising a plurality of second active circuits;
depositing a second dielectric layer over the second chip;
forming a second bonding pad in the second dielectric layer, wherein the second bonding pad is formed of the second conductive material;
stacking the first chip on the second chip, wherein the first bonding pad is in direct contact with the second bonding pad;
and
bonding the first chip and the second chip together, wherein:
the first bonding pad is electrically coupled to the second bonding pad;
and
the first active circuits are electrically coupled to the second active circuits.

12 more elements

A method comprising:

depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, wherein a top surface of the first connection pad is lower than a top surface of the first dielectric layer and the plurality of first active circuits are adjacent to a first side of the first chip;
forming a connector over the first connection pad, wherein a bottom surface of the connector is in direct contact with the top surface of the first connection pad and a top surface of the connector is level with the top surface of the first dielectric layer;
forming a first bonding pad over the first chip, wherein the first bonding pad is in direct contact with the connector and a width of the first bonding pad is greater than a width of the connector;
depositing a second dielectric layer over a second chip comprising a plurality of second active circuits adjacent to a first side of the second chip;
forming a second bonding pad in the second dielectric layer, wherein a width of the second bonding pad is greater than a width of the first bonding pad;
and
stacking the first side of the first chip on the first side of the second chip, wherein the first bonding pad is in direct contact with the second bonding pad.

4 more elements

Dependencies are inferred from the claim text.