3D integrated circuit and methods of forming the same

An integrated circuit structure comprising:

• a first die comprising:
• a top Inter-Metal Dielectric (IMD) comprising a low-k dielectric material;
• a top metal feature in the top IMD;
• an etch stop layer overlying the top metal feature and the top IMD;
• a first dielectric layer over and contacting the etch stop layer;
• a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer is porous;
• a first dielectric barrier layer over the second dielectric layer;
• and
• a first bond pad extends from a top surface of the first dielectric barrier layer to the top metal feature;
• and
• a second die comprising:
• a second bond pad bonded to the first bond pad;
• and
• a second dielectric barrier layer bonded to the first dielectric barrier layer.

An integrated circuit structure comprising:

• a first package component comprising:
• an etch stop layer;
• a first dielectric layer having a first porosity over and contacting the etch stop layer;
• a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer is porous and has a second porosity higher than the first porosity;
• a first bond pad penetrating through the first dielectric layer, the second dielectric layer and the etch stop layer;
• and
• a first dielectric barrier layer over and contacting the second dielectric layer, wherein the first bond pad is exposed through the first dielectric barrier layer, the first dielectric barrier layer has a planar top surface, and the first bond pad has a second planar top surface higher than a bottom surface of the first dielectric barrier layer;
• a second package component bonded to the first package component, wherein the second package component comprises:
• a second bond pad bonded to the first bond pad through metal-to-metal bonding;
• and
• a second dielectric barrier layer bonded to the first dielectric barrier layer.