Register file circuit and method for improving the minimum operating supply voltage

A register file circuit comprising:

• a plurality of memory cells, each of the plurality of memory cells coupled to a virtual supply voltage and a write word line;
• a plurality of header PFETs, each of the plurality of header PFETs having a gate, a source, and a drain, wherein each header PFET source is coupled to a system supply voltage, each header PFET gate is coupled to a driver circuit, and each header PFET drain is coupled to the virtual supply voltage;
• a first header NFET having a gate, a source, and a drain, wherein the first header NFET drain is coupled to the virtual supply voltage, the first header NFET gate is coupled to the driver circuit, and the first header NFET source is coupled to a ground;
• and
• a second header NFET having a gate, a source and a drain, wherein the second header NFET drain is coupled to the system supply voltage, the second header NFET gate is coupled to the driver circuit, and the second header NFET source is coupled to the virtual supply voltage.

A method of writing to a memory cell in a register file circuit, the method comprising the steps of:

• receiving a write clock signal;
• generating a pulse write signal;
• applying the pulse write signal to a first header PFET to turn OFF the first header PFET and shut off a current path from a supply voltage to a memory cell;
• applying the pulse write signal to a first header NFET and a second header NFET to turn ON the first header NFET and the second header NFET and clamp a virtual supply voltage to a threshold voltage configured to enable a write operation on the memory cell;
• and
• applying a write bit signal to the memory cell to enable the write operation on the memory cell.